1. Field of the Invention
This invention relates to a multi-layer wiring board in which connection between layers is made by a via.
2. Description of the Prior Art
In recent years, an increasingly high degree of functionalization of semiconductor devices is being required as multi-functionalization of mobile devices proceeds. Moreover, in order to meet this requirement, wiring technology of semiconductor devices is improving and miniaturization of wiring lines is advancing. A multi-layer wiring board is known as a high-density wiring technology, but as described in, for example, Japanese Unexamined Patent Application Publication No. 2004-31531 A, a diameter of a land connected to an end of an inter-layer-connecting via is generally set large with respect to a diameter of the via. In addition, a diameter of an electrode of an electronic component connected to an end of a via is similarly set large with respect to a diameter of the via.
However, in a structure where the diameter of the land is large with respect to the diameter of the via as in above-described Japanese Unexamined Patent Application Publication No. 2004-31531A, a space between lands becomes narrow. Hence, there is a problem that in cases like where a semiconductor device having narrow-pitched electrode pads such as a WLCSP (Wafer Level Chip Size Package) is built in or connected, lead-out of a wiring line from a via connected to the electrode pad is difficult. Accordingly, it is also conceivable for a space between the lands or the electrodes to be secured by setting the diameter of the land or the electrode as small as possible. However, if the diameter of the land or the electrode is set small, a contact area between the via and the land or electrode becomes small, whereby wiring resistance or connection resistance increases, or a minute positional misalignment between the land or electrode and the via causes a wiring defect or connection defect to occur.